Fpga

A few years back I wrote a RISC-V core and a DVI output demo and back then I mentioned I would add extra features to both of them. The past few years I not only updated my RISC-V core, but also combined it with the DVI output core to create basically a SOC.

The RISC-V core now can run GCC compiled code, so no need for hand written assembly code anymore. There are still several key features missing, like IRQ/Trap support (which makes it impossible to run some sort of OS at the moment).

Prettige Kerst, Merry X-Mas, of course in style, by using a Digilent Nexys Video FPGA board to control a HDMI monitor.

The idea behind this mini X-Mas holiday project was to create a GPU for my RISC-V core, so it could output things on a monitor instead only turn on/off some LED’s. Since my VHDL skills are still not that great and calculating 1920x1080 pixels at 60Hz would mean FPGA clocks up to 147MHz which leave very little room for mistakes. Since I wanted it to have a bit of a C64 feeling I reduced the internal resolution from 1920x1080 to 480x270. Also I reduced the HDMI output from 1920x1080@60 to 1920x1080@30 so everything only has to run as 74MHz.

In 2020 I made a SID player based on a Lattice MachXO2 that was connected via SPI to a STM32G4 board running Zephyr.

Now I got a Trenz SMF2000 board that has a Microsemi SmartFusion2 that has a Cortex M3 and a FPGA on one chip, so connecting the CPU to the FPGA is a lot easier. Instead of going via SPI from CPU to FPGA, it is possible to use a AHB bus to connect the CPU to the FPGA fabric. The connection from the FPGA to the SID chip still needs the 5 address + 8 data + clk + cs + rw + rst = 17 pins like with the previous setup.

One of my first projects when I started working for transtechnik (now ETC) was a DMX512 router, called E-Gate. References to that project can still be found on the ETC website. And even the windows software I wrote, called E-Gatekeeper, can still be downloaded, and it still works (even on Windows 10)

(E-gatekeeper screenshot image copyright by ETC GmbH)

The hardware was based on a Motorola (now NXP) PowerPC MPC860 CPU with a Xilinx FPGA. Back then (this was early 2000) the FPGA design was not done by me, but FPGA’s always fascinated me.

If you wish to make an apple pie from scratch, you must first invent the universe.

The famous quote from Carl Sagan could also be applied to computer science, if you want to make a program from scratch you must first invent the universe. Since I only had 2 weeks vacation, and inventing a whole universe would have been to much work, I skipped a few parts and started with designing a RISC-V core.

Prettige Kerst, Merry X-Mas, of course in style, by using a Xilinx FPGA to control a cheap 64x32 RGB LED matrix display.

I wrote a small program in VHDL that shift out a image to the RGB module and takes care of everything. After building it with Xilinx Vivado the resulting schematic looks like this;

Of course if this is not an example of how to do things for a real project, first of all the LED module lacks features like PWM control, current correction, over temperature protection, and simply the needed brightness compared to professional displays that are for example produced by my one of my clients. Secondly the VHDL is a bunch of n00b code, it doesn’t even have a way to control the display content, it just displays a static image. But since I am a C++ engineer by trade, learning an additional language that is very different in many ways isn’t a bad thing to do during a locked down X-Mas holiday.

The MOS Technology 6581/8580 SID (Sound Interface Device) is the almost 40 year old sound chip that was used in the famous Commodore 64. It uses a 5bit address / 8bit data synchronous bus with a chip select, rw, and clock signal. Since the chip uses the 1MHz (well not exactly 1MHz as I’ll explain later) clock signal also to generate all the audio frequencies, so it is important that the clock signal is stable, even though the read/write access would work fine with a unstable clock as long as the signal setup times are correct.