library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity top_level is Port ( LED0 : out std_logic; LED1 : out std_logic; LED2 : out std_logic; LED3 : out std_logic; LED4 : out std_logic; LED5 : out std_logic; LED6 : out std_logic; LED7 : out std_logic; DIP_SW0 : in std_logic; DIP_SW1 : in std_logic; DIP_SW2 : in std_logic; DIP_SW3 : in std_logic; PB0 : in std_logic; PB1 : in std_logic; PB2 : in std_logic; PB3 : in std_logic; BB_CLK : in std_logic; BB_CLK_EN : out std_logic; JA0_1_P : out std_logic; -- JA - Pin 1 r0 JA0_1_N : out std_logic; -- JA - Pin 2 r1 JA2_3_P : out std_logic; -- JA - Pin 3 g0 JA2_3_N : out std_logic; -- JA - Pin 4 g1 JA4_5_P : out std_logic; -- JA - Pin 7 b0 JA4_5_N : out std_logic; -- JA - Pin 8 b1 JA6_7_P : out std_logic; -- JA - Pin 9 le JA6_7_N : out std_logic; -- JA - Pin 10 oe JB0_1_P : out std_logic; -- JB - Pin 1 A JB0_1_N : out std_logic; -- JB - Pin 2 B JB2_3_P : out std_logic; -- JB - Pin 3 C JB2_3_N : out std_logic; -- JB - Pin 4 D JB4_5_P : out std_logic; -- JB - Pin 7 clk JB4_5_N : out std_logic; -- JB - Pin 8 JB6_7_P : out std_logic; -- JB - Pin 9 JB6_7_N : out std_logic -- JB - Pin 10 ); end top_level; architecture behavioral of top_level is signal r_o : STD_LOGIC_VECTOR (1 downto 0); signal g_o : STD_LOGIC_VECTOR (1 downto 0); signal b_o : STD_LOGIC_VECTOR (1 downto 0); signal line_sel_o : STD_LOGIC_VECTOR (3 downto 0); signal clk_o : STD_LOGIC; signal le_o : STD_LOGIC; signal oe_o : STD_LOGIC; signal clk_i : STD_LOGIC; signal rst_i : STD_LOGIC; signal clk_buf : std_logic; signal next_clk : std_logic; signal bit_cntr : integer range 0 to 63; signal next_bit_cntr : integer range 0 to 63; signal line_cntr : integer range 0 to 15; signal next_line_cntr : integer range 0 to 15; signal r_buf : std_logic_vector(1 downto 0); signal g_buf : std_logic_vector(1 downto 0); signal b_buf : std_logic_vector(1 downto 0); signal next_r_buf : std_logic_vector(1 downto 0); signal next_g_buf : std_logic_vector(1 downto 0); signal next_b_buf : std_logic_vector(1 downto 0); type state_type is (st_init, st_shift_clk_low, st_shift_clk_high, st_output_disable, st_latch, st_output_enable); signal state, next_state : state_type; type fb_type is array (31 downto 0) of std_logic_vector(255 downto 0); signal fb : fb_type := ( (X"1111111111111111111111111111111111111111111111111111111111111111"), (X"1222222222222222222222222222222222222222222222222222222222222221"), (X"1200000000000000000000000000000000000000000000000000000000000021"), (X"1200777000000000000070007000000000000000000000000000000066060021"), (X"1200700707070007700077007700700000000077000000000000000000006021"), (X"1200777007707070070070007000000077700700700000000000000066060021"), (X"1200700007000077770070007000700700700777700000000000000000000021"), (X"1200700007000070000070707070700700700700000000000000000066066021"), (X"1200700007000007700007000700700077700077700000000000000000000021"), (X"1200000000000000000000000000000000700000000000000000000000000021"), (X"1200000000000000000000000000000700700000000000000000000000000021"), (X"1200000000000000000000000000000077000000000000000000000000000021"), (X"1200000000000000000000000000000000000000000000000000000000000021"), (X"1200000000000000000000000000000000000000000000000000000000000021"), (X"1200000000050000000000000000000000000000000000000000000000000021"), (X"1200000000555000000000000000000070000000000000000000007000000021"), (X"1200000000020000000000000000000070000007700707000777007700000021"), (X"1200000000222000000000000000000070070070070770707000007000000021"), (X"1200000022222220000000000000000077700077770700000777007000000021"), (X"1200000002222200000000000000000070700070000700000000707070000021"), (X"1200000022222220000000000000000070070007700700000777000700000021"), (X"1200002222222222200000000000000000000000000000000000000000000021"), (X"1200000222222222000000000000000000000000000000000000000000000021"), (X"1200002222222222200000000000000000000000000000000000000000000021"), (X"1200222222222222222000000000000000000000000000000000000000000021"), (X"1200000000333000000000000000000000000000000000000000000000000021"), (X"1200000000333000000000000000000000000000000000000000000000000021"), (X"1200077777777777770000000000000000000000000000000000000000000021"), (X"1277777777777777777777777777000000000000000000000000000000000021"), (X"1277777777777777777777777777777777770000000000000000000000000021"), (X"1222222222222222222222222222222222222222222222222222222222222221"), (X"1111111111111111111111111111111111111111111111111111111111111111") ); signal le_buf : std_logic; signal next_le_buf : std_logic; signal oe_buf : std_logic; signal next_oe_buf : std_logic; signal line_sel_buf : std_logic_vector(3 downto 0); signal next_line_sel : std_logic_vector(3 downto 0); signal clk_div : unsigned(4 downto 0); function get_bit(y : integer; x : integer; color : integer ;buf: fb_type) return std_logic is begin return buf(31 - y)(255 - ((x * 4) + (3 - color))); end function; begin BB_CLK_EN <= '1'; process (BB_CLK) begin if (rst_i = '1') then clk_div <= (others => '0'); elsif (rising_edge(BB_CLK)) then clk_div <= clk_div + 1; end if; end process; clk_i <= clk_div(4); rst_i <= PB0; JA0_1_P <= r_o(0); JA0_1_N <= r_o(1); JA2_3_P <= g_o(0); JA2_3_N <= g_o(1); JA4_5_P <= b_o(0); JA4_5_N <= b_o(1); JA6_7_P <= '0'; JA6_7_N <= '0'; JB0_1_P <= line_sel_o(0); JB0_1_N <= line_sel_o(1); JB2_3_P <= line_sel_o(2); JB2_3_N <= line_sel_o(3); JB4_5_P <= clk_o; JB4_5_N <= le_o; JB6_7_P <= oe_o; JB6_7_N <= '0'; LED0 <= PB0; LED1 <= PB1; LED2 <= PB2; LED3 <= PB3; LED4 <= DIP_SW0; LED5 <= DIP_SW1; LED6 <= DIP_SW2; LED7 <= DIP_SW3; process(clk_i, rst_i) begin if (rst_i = '1') then line_cntr <= 0; bit_cntr <= 0; state <= st_init; oe_buf <= '0'; le_buf <= '0'; clk_buf <= '0'; r_buf <= (others => '0'); g_buf <= (others => '0'); b_buf <= (others => '0'); line_sel_buf <= (others => '0'); elsif (rising_edge(clk_i)) then line_cntr <= next_line_cntr; bit_cntr <= next_bit_cntr; state <= next_state; oe_buf <= next_oe_buf; le_buf <= next_le_buf; clk_buf <= next_clk; r_buf <= next_r_buf; g_buf <= next_g_buf; b_buf <= next_b_buf; line_sel_buf <= next_line_sel; end if; end process; process(line_cntr, bit_cntr, state, oe_buf, le_buf, clk_buf, r_buf, g_buf, b_buf, fb, line_sel_buf) begin next_state <= state; next_line_cntr <= line_cntr; next_bit_cntr <= bit_cntr; next_oe_buf <= oe_buf; next_le_buf <= le_buf; next_clk <= clk_buf; next_r_buf <= r_buf; next_g_buf <= g_buf; next_b_buf <= b_buf; next_line_sel <= line_sel_buf; case state is when st_init => next_le_buf <= '0'; next_oe_buf <= '0'; next_line_cntr <= 0; next_bit_cntr <= 0; next_clk <= '0'; next_state <= st_shift_clk_low; next_line_sel <= (others => '0'); next_r_buf(0) <= get_bit(0, 0, 0, fb); next_r_buf(1) <= get_bit(0 + 16, 0, 0, fb); next_g_buf(0) <= get_bit(0, 0, 1, fb); next_g_buf(1) <= get_bit(0 + 16, 0, 1, fb); next_b_buf(0) <= get_bit(0, 0, 2, fb); next_b_buf(1) <= get_bit(0 + 16, 0, 2, fb); when st_shift_clk_low => next_le_buf <= '0'; next_clk <= '1'; next_state <= st_shift_clk_high; when st_shift_clk_high => next_clk <= '0'; next_le_buf <= '0'; if (bit_cntr >= 63) then next_state <= st_output_disable; next_oe_buf <= '0'; next_bit_cntr <= 0; else next_oe_buf <= '1'; next_state <= st_shift_clk_low; next_bit_cntr <= bit_cntr + 1; end if; next_r_buf(0) <= get_bit(line_cntr, bit_cntr + 1, 0, fb); next_r_buf(1) <= get_bit(line_cntr + 16, bit_cntr + 1, 0, fb); next_g_buf(0) <= get_bit(line_cntr, bit_cntr + 1, 1, fb); next_g_buf(1) <= get_bit(line_cntr + 16, bit_cntr + 1, 1, fb); next_b_buf(0) <= get_bit(line_cntr, bit_cntr + 1, 2, fb); next_b_buf(1) <= get_bit(line_cntr + 16, bit_cntr + 1, 2, fb); when st_output_disable => next_oe_buf <= '0'; next_le_buf <= '1'; next_bit_cntr <= 0; next_state <= st_latch; if (line_cntr >= 15) then next_line_cntr <= 0; else next_line_cntr <= line_cntr + 1; end if; when st_latch => next_oe_buf <= '0'; next_le_buf <= '0'; next_bit_cntr <= 0; next_state <= st_output_enable; if (line_cntr = 0) then next_line_sel <= "1111"; else next_line_sel <= std_logic_vector(to_unsigned(line_cntr - 1, next_line_sel'length)); end if; when st_output_enable => next_bit_cntr <= 0; next_le_buf <= '0'; next_oe_buf <= '1'; next_clk <= '0'; next_state <= st_shift_clk_low; next_r_buf(0) <= get_bit(line_cntr, 0, 0, fb); next_r_buf(1) <= get_bit(line_cntr + 16, 0, 0, fb); next_g_buf(0) <= get_bit(line_cntr, 0, 1, fb); next_g_buf(1) <= get_bit(line_cntr + 16, 0, 1, fb); next_b_buf(0) <= get_bit(line_cntr, 0, 2, fb); next_b_buf(1) <= get_bit(line_cntr + 16, 0, 2, fb); when others => next_state <= st_init; end case; end process; r_o <= r_buf; g_o <= g_buf; b_o <= b_buf; line_sel_o <= line_sel_buf; clk_o <= clk_buf; le_o <= le_buf; oe_o <= not oe_buf; end behavioral;